A participant of e-BRAINS is contributing to a SEMATECH workshop together with other experts in the field of 3D integration. The title of the workshop is "Underfill Challenges for 3D Interconnect" and it will take place at Doubletree by Hilton 2050 Gateway Place San Jose, California on 9 November, 2012. The event will be open by
Peter Ramm, Fraunhofer EMFT Munich and has the following agenda:
8:00 AM – 8:30 AM Registration and Continental Breakfast
8:30 AM – 8:45 AM Welcome; Peter Ramm, Fraunhofer EMFT Munich
8:45 AM – 9:00 AM The Role of SEMATECH; Brian Sapp, SEMATECH
9:00 AM – 9:40 AM 3DIC Markets and Technology Drivers; Charles Woychik, Invensas
9:40 AM – 10:20 AM Challenges Related to Underfill for European Activities on 3D Integration; Maaike M. V. Taklo, SINTEF
10:20 AM – 10:35 AM Break
10:35 AM – 11:15 AM Thermal Challenges for 3D; Ken Goodson, Stanford University
11:15 AM – 11:55 AM Automated Thermo Mechanical Modeling of 3D Chip Stacking; Kamal Karimanal, Cielution LLC
11:55 AM – 1:00 PM Lunch
1:00 PM – 1:40 PM The Current Capabilities and Future Challenges of Acoustic Microscopy (AM) for 3D Interconnect Underfill Inspection; Steven Marvell, Sonoscan
1:40 PM – 2:20 PM X-Ray Microscopy: The Ultimate Inspection Technology for 3D IC Packaging; Yuri Sylvester, Xradia
2:20 PM – 3:00 PM 2012 Industry Survey Results: Underfill Challenges for High Volume Manufacturing; Sunoo Kim, SEMATECH
3:00 PM – 3:30 PM Discussion and Wrap-Up
The e-BRAINS' project partners have contributed to the 13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems EuroSimE 2012 Lisbon, Portugal, April 16-17-18, 2012 delivering the keynote  and paper . The EuroSimE 2012 held in Lisbon organized locally by ISQ (E. Dias Lopes) was a successful event with more than 150 registered participants.
 "Determination of Interface Fracture Parameters by Shear Testing Using Different Theoretical Approaches" R. Dudek 1, B. Brämer 1, J. Auersperg 1, R. Pufall 2, H. Walter 3, B. Seiler 4, B. Wunderle 5; 1 Fraunhofer ENAS, Micro Materials Center Chemnitz, Germany 2 Infineon Technologies, Munich, Germany 3 Fraunhofer IZM, Berlin, Germany 4 CWM GmbH, Chemnitz, Germany 5 TU Chemnitz, Germany
 "Increasing the Robustness for Reliable Packages by Prediction of Delamination by Cohesive Zone Element Simulation" R. Pufall 1, M. Goroll 1, W. Kanert 1, R. Dudek 2; 1 Infineon Technolgies AG, Neubiberg 2 Fraunhofer ENAS, Chemnitz
Alan Mathewson (Tyndall Institute, Ireland) has delivered the Keynote Talk "Status of Research and Application Development of 3DIC Technology in Europe" at the IEEE International 3D System Integration Conference (3DIC
) Osaka on Feb 1, 2012:
You can find the presentation here
International 3D System Integration Conference
January 31-February 2, 2012, Osaka
The IEEE International 3D System Integration Conference (3DIC) will be held at the "Senri Life-Science center" Osaka on January 31-February 2, 2012.
This conference combines the previous ASET and IEEE EDS Society sponsored International 3D System Integration Conference, held in Tokyo in 2007 & 2008 and the Fraunhofer and IEEE CPMT sponsored International 3D System Integration Workshop held in 2003 & 2007 in Munich. After the first combined conference in San Francisco 2009, the 2nd IEEE 3D System Integration Conference was held in Munich in 2010. The 3rd conference will be held in Osaka in 2011, rotate to San Francisco in 2012 and then rotate back to Munich in 2013.
3DIC 2011 will cover all 3D integration topics, including 3D process technology, materials, equipment, circuits technology, design and test methodology and applications. The conference invites authors and attendees to submit and interact with 3D researchers from all around the world. Papers are solicited in subject topics, including, but not limited to, the following:
3D Integration Technology. Through Silicon Vias (TSV), wafer thinning, wafer alignment, wafer bonding, wafer dicing, 3D IC process, monolithic 3D integration, heterogeneous 3D integration (e.g. for MEMS, NEMS), capacitive coupling, inductive coupling, multilevel epitaxial growth, etc.
3D IC Circuits Technology. 3D SOC, 3D Memory, 3D Processor, 3D DSP, 3D FPGA, 3D RF and microwave/millimeter wave, 3D analog circuits, 3D biomedical circuits etc.
3D Applications. Imaging, memory, processors, communications, networking, wireless, biomedical, MEMS/NEMS etc.
3D Design and Test Methodology. 3D CAD, 3D synthesis, 3D design flows, Signal and power integrity analysis and design in 3D, 3D thermal design and analysis, test and design for test; 3D mechanical stress and reliability design and analysis, etc.
Presentation abstracts and proposals for panels and tutorials should be submitted on the conference web site: www.3dic-conf.jp. Deadline for papers and proposals is October 31, 2011. Abstracts are to be one-page text with one-page of figures and drawings. Accepted papers will be due December 14th, 2011.
C/O Inter Group Corp.
Akasaka-sanno Square Bldg 2-2-12 Akasaka
Minato-ku, Tokyo 107-0052, Japan